An Automated SerDes Frontend Generator Verified With a 16-nm Instance Achieving 15 Gb/s at 1.96 pJ/bit

In this letter, we present the design methodology embedded within a SerDes frontend generator along with experimental results from an instance produced in TSMC 16 nm. A generator is an automated, parameterized design procedure that produces schematics and layouts based on top-level performance and architecture specifications. A half-rate current-integration SerDes instance was generated in TSMC 16-nm technology with passive CTLE, 1-tap FFE, and 4-tap DFE equalization. The instance operates at 15 Gb/s with BER less than 1E-12, and consumes 29.4 mW (1.9 pJ/bit) from 0.8-V/0.9-V supplies.