A FPGA-Based SIFT Architecture for Motion Estimation in Video Coding

In multi-view video coding (MVC), inter-view and temporal redundancies worsen coding efficiency and video quality, and they are needed to eliminate. Motion Estimation (ME) is a key factor for high quality video coding to reducing complexity. This paper proposes a parallel hardware architecture for computing ME by using scale-invariant feature transform (SIFT). It has advantages over many other algorithms because features that detected are fully invariant to image scaling and rotation. This paper applies Fast Fourier Transform (FFT) to reduce the complexity in SIFT algorithm. SIFT feature is used to matching corresponding point to find the search range. The experimental results shown that the hardware architecture for SIFT algorithm realized fast feature extraction, and reduces the computational load and memory.