Characterization of Deep and Shallow Traps in GaN HEMT Using Multi-Frequency C-V Measurement and Pulse-Mode Voltage Stress

In this paper, the influence of interface traps at the SiN/GaN interface and carbon-related buffer traps on GaN high electron mobility transistor (HEMT) on silicon substrate has been studied using high-frequency capacitance-voltage (HFCV) and quasi-static C-V (QSCV) measurement. The correlation between dynamic resistance degradation and trap density distribution subjected to pulse stress conditions has been examined. Deeper-level traps from the hole-emission process of the carbon-related buffer layer are activated by high drain voltage during off-state stress, and shallow-level traps at the SiN interface are enhanced by an increase in gate voltage during the on-state stress. 2-D device simulations have been carried out to probe the physical insight into the dynamic resistance degradation. Good agreement between experimental data and simulated results is obtained while taking into account shallow-level and deeper-level traps.