Analysis and Suppression Strategy for the Double-Line Frequency Pulsation in Single-Phase Quasi-Z-Source Converter

Devices and the passive components in the single-phase impedance source network converter are sensitive to the double-line-frequency (DLF) pulsation. Previous research works have studied the power decoupling and the DLF equivalent model for the power pulsation suppression method. This paper explored the DLF transfer routes in the impedance source network. A comprehensive stress derivation of the passive components and switching devices are obtained for the suppression method enhancement and optimization. For the DLF passive suppression method, the explanation for the passive component volume issue is provided from the stress aspect. The component value solution space and corresponding design guidance are presented. For the DLF active suppression method (ASM), a buck-type dc-side ASM suppression method is employed and its optimization is demonstrated with the assistant circuit stress analysis. The total capacitor and inductor values get reduced by 77% and 25%, respectively. The corresponding pulsewidth modulation method implementation and the common-mode leakage current demonstration are also presented. The effectiveness of the theoretical analysis and optimization methods is verified by simulations and experiments.