Design for Calibratability of a N-Integer Low-Frequency Phase-Locked Loop

Process variations in MOS manufacturing processes tend to increase within each new technology node, leading to lower production yields, particularly those of analogue circuits, which are also sensitive to external perturbations that might force there performance to drift beyond there admissible tolerance margins. This issue is addressed here with the design of a calibratable N-Integer phase-locked loop (PLL) based frequency synthesizer. In the approach being proposed, a statistical analysis is carried out to know the sensitivity of the PLL performance to expected process, temperature, and voltage variations. A training data set is then identified and used to define the calibration law and the required calibration algorithm. Simulation results are presented that confirm its validity.