Security-oriented Code-based Architectures for Mitigating Fault Attacks

Error-detecting codes (EDCs) are an efficient and versatile tool to detect disturbances during the operation of a circuit. Historically, EDCs were considered in the context of reliability and safety, where failures were assumed to occur due to natural reasons, like noise or ageing. However, they have also been suggested in the security context, as an approach to counteract malicious physical attacks on cryptographic and other security-critical circuits. In this paper, we review recently developed security-oriented code constructions, pointing out the differences in assumptions and efficiency metrics for reliability- and security-oriented EDCs. We propose a number of architectures to apply these findings to actual cryptographic circuits. Experimental results obtained using a fault injector on an FPGA board demonstrate the detection and correction performance of the architectures.