CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder

This brief describes a novel architecture for vertical-cavity surface emitting laser (VCSEL) array driver. It is designed in a 40 nm CMOS process and is dedicated for SPAD-based direct time-of-flight rangefinding. The architecture is based on charge transfer between an integrated capacitance and the VCSEL array with a voltage doubler implementation to ensure the generation of sub-nanosecond current pulses at high frequency. The results obtained from post-layout simulations shows an achievable peak current higher than 200 mA at 500 ps current pulse width and a 180 mA peak current at 250 ps pulse width. The proposed power architecture is operated up to 330 MHz at a supply voltage of 2.5 V. The circuit occupies a total area of 250×280 μm
²
.