Design & Analysis of Asynchronous (Clockless) Circuits and Implementation using Mentor Graphics ASIC Design Tools

Low power consumption is always a goal in the design and manufacture of digital circuits. It allows increases in performance, stability, better operational costs and overall battery time among other benefits. Many low power design techniques have been proposed in the past for clocked designs. However, the clock itself is a major element which consumes power and produces heat. The latest trend in low power design approach is to eliminate the clock source from the architecture as it consumes most of the power. This is known as asynchronous design. The prime focus of this study was to utilize existing ASIC design tools for design and analysis of asynchronous circuits. The circuits are implemented with the help of a hardware description language (HDL) using Delay Insensitive Minterm Synthesis (DIMS) technique and simulated using Mentor Graphics ModelSim. Four phase, dual-rail asynchronous design protocol is used. The results showed that four phase, dual-rail clockless circuits using Muller-C element are easy to implement through HDL language using DIMS technique, because it is simple for synthesis of dual rail functional blocks and the advantage is that the designs are strong condition Quasi Delay Insensitive (QDI). Furthermore it has been established that an existing ASIC design tool flow can be used to design clockless circuits on a larger scale.