A Shortest Path Algorithm for 3D Integrated Circuit TSV Assignment

In 3-D integrated circuits (3-D ICs), through silicon via (TSV) is a complex arrangement of vertical interconnects used to connect die-to-die, die-to-wafer, and wafer-to-wafer. However, routing and placement challenge of TSV in industry is one of vital barrier to adopt the 3-D ICs technology. When ICs are stacked in 3D structure, inter layer wire length and congestion becomes a major problem. In this paper, the algorithm for finding shortest path in 3D net has been optimized and modified. The modified algorithm uses Manhattan distance and is implemented using binary heap instead of priority queue. The simulation results show that the modified routing algorithm achieves 3k lesser execution time reduction compared with the available routing algorithms.