Low-Latency K-Means Based Multicast Routing Algorithm and Architecture for Three Dimensional Spiking Neuromorphic Chips

As the scale of Spiking Neural Networks (SNNs) grows, the inter-neuron connection problem becomes one of the major design considerations of SNN-based hardware. To deal with this issue, many researchers have studied Network-on-Chips (NoCs) with tree-like topologies to easily support one-to-many communication method in SNNs. However, such network suffers from high congestion, especially under the bursting activity of SNNs. In this paper, we introduce a novel multicast routing algorithm and 3D-NoC architecture for spiking neuromorphic chips. The proposed routing method alleviates the congestion of the overall SNN system by adopting a K-means clustering scheme, which divides the network into balanced partitions. The proposed algorithm, named KMCR, is integrated into our 3DNoC-SNN
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system and was validated based on an RTL-level implementation, while the area/power analysis is performed using 45-nm CMOS technology. The experimental results show that the proposed algorithm achieves about 14.43% lower latency and 24.5% higher throughput when compared to the XYZ-unicast multicast for 3D-NoC configuration. Furthermore, the system achieves 8.7% higher spike injection rate when compared to other exiting works.