Implementation of high speed Reed-Solomon decoder

Today the digital coded systems for either data transmission or data storage are much in common. The output of the channel or storage medium differs from its input because they are both sensitive to the errors that can result from impaired transmission. For that reason, Reed-Solomon (RS) codes are commonly used in various applications. In this paper, we propose the VLSI implementation of Reed-Solomon decoder with the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. We analyzed the RS decoding algorithm for the efficient parallel and pipelined structure and modified the Euclid's algorithm arithmetic part to apply the parallel structure. The overall RS decoder is compared to Shuo's. We show the 10% area efficiency increase over Shao's time domain decoder and three times faster operation. In addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemented with LG 0.6 processing.