VHDL implementation of 2-D median filter

An 8-bit VHDL based 2-D median filter is designed using Mentor Graphics tools. The algorithm is based on sorting pixel samples and extracting their median values. The VHDL code was written, synthesized and optimized for an IC layout using CMOS 2micron technology. A MatLab program for this algorithm was written, tested and verified on several 400/spl times/400 images. The paper details the algorithm and CAD tool processing. This paper is considered as a building block for the development of post-processing Application Specific Integrated Circuits (ASIC) base system for video decompressed signals.