A Low-Cost Self-Test Architecture Integrated With PRESENT Cipher Core

Cryptographic cores integrated with self-test ability fulfill both data security and reliability requirements of the Internet of Things (IoT) network. However, from the IoT perspective where most devices are resource constrained, a fundamental problem associated with most of the self-test architectures is high hardware overhead due to the additional circuit for self-test operation. This paper presents the design of a low-cost self-test architecture and its integration with the PRESENT cipher core. The hardware overhead of the proposed low-cost self-test architecture is reduced by adopting two key strategies: 1) using hardware-efficient X-Compactor technique for test response compaction and 2) reusing the PRESENT cipher core as a Test Pattern Generator (TPG). The proposed self-test architecture is implemented on different Xilinx Field Programmable Gate Array (FPGA) platforms and devices. Analysis of the implementation results shows that the proposed self-test method occupies 23% less hardware area overhead and provides 14% higher throughput per slice performance with the fault coverage of over 99% compared with the existing self-test designs. The resulting analysis indicates that the proposed self-test design is one of the most viable testing solutions for resource-constrained IoT devices.