Strength-Varying keeper based 4:1 MUX for low-leakage and low jitter at 500 MHz Clock

High speed, less area over static CMOS, makes domino circuits more popular in recent trends of VLSI system.But these domino circuit suffer from high contention and leakage current which increases significantly in wide fan-in gates with increase in parallel legs. In this paper, an approach for reducing leakage current and contention current is presented by varying the strength of keeper transistor. The keeper is controlled by a control signal generator that helps in storing the charge at dynamic node irrespective of applied input. These leads to reduction of contention current between evaluation network and keeper. The sleep transistor further helps in reducing leakage. 4:1 Multiplexer circuit is implemented using strength varying keeper technique reflecting low leakage, high speed and better performance with less jitter and attenuation at 500 MHz clock compared to conventional literature domino technique using 90 nm technology.