Warpage Prediction and Optimization for Embedded Silicon Fan-Out Wafer-Level Packaging Based on an Extended Theoretical Model

The fan-out package is designed to provide increased I/O density within a reduced form factor at a lower cost, as well as good electrical performance and heterogeneous integration capabilities, which has gained significant attention in recent years. However, warpage control during manufacturing process is a key character for fan-out packages. This paper focuses on the warpage prediction and optimization of embedded silicon fan-out (eSiFO) wafer-level package. An extended theoretical calculation model is applied and demonstrated, and the effects of various parameters on warpage were analyzed for optimization. By comparison with the experimental results, the finite-element modeling (FEM) simulation results and classic bimaterial model, the proposed extended theoretical calculation model is proven to be simple, fast, and effective for eSiFO wafer-level package. The effects of process steps, structural parameters, and material parameters were studied based on the extended theoretical model, and some advice on reducing warpage was given in the end. This paper offers an insight work for the warpage study of other embedded and fan-out packages.