Analysis and elimination of third harmonic oscillation in capacitor voltages of 3-level voltage source converters

Capacitor voltages on the DC side of a three-level voltage source power converter must be equal in order to avoid excessive harmonic generation and voltage stresses on the power converter valves. This paper analyses a particular type of capacitor voltage imbalance: the steady-state third harmonic oscillation where the two capacitor voltages are 180/spl deg/ out of phase and the total DC voltage remains constant. A method to eliminate this harmonic for converters used in DC power transmission is suggested and its effectiveness is confirmed by digital simulation.