A Novel Approach for Reversible Realization of 3:8 Decoder Circuit with Optimized Performance Parameters

Reversible realization of digital circuits basically aims for the low loss efficient computing systems. Among combinational digital circuits, decoders are considered as one of the most useful circuit. Till now, many design approaches have been already proposed by various researchers for the reversible realization of decoder circuits. Here, in this paper we have proposed a novel approach for the Reversible realization of 3:8 size decoder circuit with optimized performance parameters as compared to the earlier designs. The comparison is done in terms of total number of Reversible logic gates, constant inputs, garbage outputs and quantum cost. This design may be further explored for other low power applications.