Evaluation of Bulk and SOI FeFET Architecture for Non-Volatile Memory Applications

The stress induced by the capping electrode is critical to stabilizing the ferroelectric phase in Si-doped HfO
₂
which is being actively explored for embedded non-volatile memory applications. While TiN is commonly used as the electrode of choice owing to its thermodynamic stability with HfO
₂
, its work function (WF) (=4.8eV) results in reduced memory window (MW), and higher interlayer field (EIL) in bulk Ferroelectric FETs (FeFETs). This is attributed to the built-in electric-field that arises from the WF difference between the metal and the semiconductor. This effectively reduces the ferroelectric hysteresis, and thus, the MW at the read current. Optimizing the MW and the EIL would entail changing the WF, and thus, the capping electrode-essential to retaining the desired ferroelectric properties. We, therefore, propose using the silicon on insulator (SOI)-FeFET architecture which provides an additional knob-back-gate bias (V
_bg
)-to optimize the MW while reducing the E
_IL
. Further, we show that unlike the bulk FeFET, where a small deviation from the optimal WF dramatically shrinks the MW, the SOIFeFET facilitates a relatively constant MW over a wide range of V
_bg
. Thus, the SOI-FeFET simplifies the MW & EIL optimization and provides an improved MW versus E
_IL
trade-off in comparison to the bulk FeFET.