Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse

The Hadamard-based Sum of Absolute Transformed Differences (SATD) is a distortion metric that correlates better with other video encoding steps than the commonly used Sum of Absolute Differences (SAD) and thus potentially improves coding efficiency. However, due to the Hadamard Transform (HT), it demands a large share of total encoding time. Meanwhile, the widespread use of embedded encoders made computational complexity and energy efficiency two relevant issues, besides the usual trade-off between the rate and distortion. Hence, the adoption of SATD during video coding requires the design of energy-efficient hardware accelerators. In this paper, we show that the SATD improves coding efficiency by up to -2.99% in BD-Rate when used in motion estimation within the HEVC Model (HM). Subsequently, as the main contribution, we combined two properties featured by the SATD to devise a novel hardware architecture based on calculation reuse. These properties allow for rearranging the architecture components to reduce the hardware size, save operations, and thus, reduce energy. The synthesis and simulation results indicate that the proposed architecture can lead to area and energy savings of about 28% and 32%, respectively, compared to the state-of-the-art architecture based on reuse solely.