A Dependency-Free Real-Time UHD Architecture for the Initial Stage of HEVC Motion Estimation

Novel coding tools and algorithms were proposed in the High Efficiency Video Coding Standard (HEVC), and are still being proposed over the HM reference software in order to achieve a better compression efficiency, decrease encoding time, make its stages suitable for hardware implementation, and other independent improvements. Particularly, for the initial stage of the motion estimation (ME) process, the Advanced Motion Vector Prediction (AMVP) and the Dynamic Search Range (DSR) algorithms were introduced in the field targeting the determination of the motion vector predictor (MVP), also used as the search center, and search range (SR), which are parameters needed in the subsequent steps of motion estimation (ME). However, the significant complexity of these new tools enhances the need to develop hardware (HW) accelerators. Furthermore, in the field of HW architectures for video compression, techniques that solve dependency problems (which are detrimental to performance) — in this case, between sub-stages of ME— were proposed by some authors. Thereupon, an integrated and synchronized dependency-free HW architecture for the initial stage of the ME process — regarding MV prediction and SR calculation— is proposed in this paper. Synthesis results on a middle ground FPGA (Kintex-7 xc7k70tfbv676-1) show that the integrated architecture can achieve a throughput up to 8K at 72 frames-per-second (4:2:2 subsampling) while using a maximum of 7.04% of the FPGA resources (on slice LUT’s).