Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Arrays of vortex transitional (VT) memory cells with functional density up to 1 Mbit/cm
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have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-μA/μm
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MIT LL fabrication process SFQ5ee with eight niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied 168 μm
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, resulting in an over 0.5 Mbit/cm
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functional density. Then, we reduced the cell area down to 99 μm
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(corresponding to over 0.9 Mbit/cm
²
functional density) by utilizing self-shunted Josephson junctions (JJs) with critical current density JC of 600 μA/μm
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and eliminating shunt resistors. The fabricated high-JC memory cells were fully operational and possessed wide read/write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: 1) miniaturization of superconducting transformers by using soft magnetic materials; and 2) reduction of JJ area by using planar high-JC junctions similar to variable thickness bridges.