Reduced modified T-type topology for cascaded multilevel inverters

Multilevel inverters are applied in medium-voltage high power applications, nowadays. The drawback of multilevel inverters is required for a high number of power electronics devices to generate more voltage levels in order to reduce THD's magnitude. This paper presents a reduced T-type topology for a cascaded multilevel inverter. The main advantages of the proposed topology are reducing the switching elements and the total blocking voltage for generating a high number of levels. A comprehensive comparison is done with other similar multilevel inverter topologies to show the superiority of the reduced topology. The performance of the reduced multilevel inverter is presented for a 61-levels cascaded topology.