A High-Precision 2.5-ps RMS Time Synchronization for Multiple High-Speed Transceivers in FPGA

The high-speed serial transceiver plays a key role in the high-speed data transmission. Because of the independent clock network in each transceiver, there exist random skews between the multiple transceivers each time the system reinitializes. In the system of data transmission, these random skews are always permitted and the intrachannel synchronization is guaranteed by inserting some same comma codes in each channel. However, for the strict clock distribution system, these random skews are unacceptable. To address this problem, a scheme combined of a tunable phase interpolator (PI) and a high-precision time-to-digital converter (TDC) is presented. A plain TDC is employed to measure the skews of parallel clocks in multichannels with bin size of ~10.2 ps and precision of ~18.0 ps. The method of multiple measurements average is adopted to further improve the TDCs performance. On this basis, time synchronization with root mean square (rms) of ~2.5 ps and peak-to-peak value of ~14.7 ps is implemented in a 20-nm fabrication process ultrascale field programmable gate array (FPGA). Compared to the measured results (rms of ~22 ps and peak-to-peak value of ~105 ps) of the Xilinx self-phase alignment method, the presented scheme has more than six times performance improvement. In addition, this scheme can lock the delay between different channels to arbitrary configurable offsets, making it very suitable for scenarios where multichannel latencies are strictly restricted.