Packet Filtering for IPV4 Protocol Using FPGA

Firewall is a key domain of security and a necessity for every organization. The basic function of firewall is packet filtering. This paper makes use of highly parallelized architecture of FPGA. The packet filtering is done for IPv4 protocol by forming rule set for allowed incoming and outgoing IP address. The packet takes one clock cycle time for delivering the output packet despite increasing number of rules. All the rules are simultaneously check in the system. The hardware firewall is better than software firewall in terms of speed and security.