Design of Output Capacitorless Low Dropout Regulator with Fast Transition Response

A linear low dropout (LDO) voltage regulator with an enhanced transition response is presented in this paper. The proposed circuit used a folded cascode structure for error amplifier which provides high gain. An enhancer circuit which consists of an inverter and NMOS, will provide a less resistance path for discharging during transition time to fasten up the switching process is implemented. The designed LDO is implemented in CMOS 180nm technology for an input voltage of 1.8V, with dropout voltage of 200mV, providing load current of 50mA over 50pF load capacitance, and consuming only 2l.89μA of quiescent current. The simulation results of the design shows that the load and line regulation are: 2.4μV/mA and 65mV/V, respectively, and the phase margin is of 56.4078deg at 922.56 KHz of unity gain frequency. The proposed LDO has attained a settling time of 10ns when the load switches from 0 to 50mA in 250ps.