25.1 A 562F2 Physically Unclonable Function with a Zero-Overhead Stabilization Scheme

Internet of Things (IoT) devices bring a growing demand for secure, low-power, and low-cost secret key and ID storage solutions. Physically unclonable functions (PUFs) are one of the most promising alternatives to conventional non-volatile memory (NVM) solutions, which usually incur extra cost and are vulnerable to physical attackers. In recent years, significant research efforts have been devoted to improving the stability of PUF responses/keys across PVT variations, while maintaining the low-cost and low-power benefits. PUF design involves circuit topologies, stabilization methods, and error correction schemes. While redundancy-based stabilizing methods, such as extensive unstable bit masking and error correction codes (ECCs), are powerful to achieve 100% reliable keys [1,2,7], the on-chip area cost for redundancy, energy and latency during key extraction, and testing cost grow super linearly with the percentage of unstable bits in most cases (Fig. 25.1.1). Therefore, PUF designs with native reliability and lossless stabilizing methods are desirable. PUFs using metastability are fast and efficient [1,2], but suffer from transient noise. PUFs relying on shared digitizers [3,4] save area but require accurate comparators and suffer from noise during readout. PUF cells with static operation and local digitizing are shown to achieve the best stability [5-7], among which the amplifier chain structure shown in Fig. 25.1.1 demonstrates best native stability and low cost [6-7]. A NAND-based design [7] suffers from high power consumption and large area, while a 2T amplifier-based PUF [6] achieves a good trade-off among desired properties. However, the 2T amplifier in [6] does not scale well with technology, limited by its amplification gain and asymmetrical headroom (Fig. 25.1.1, top right). In this paper, a 562F
²
PUF cell, which can be reconfigured to a different PUF cell locally for lossless stabilization with zero area overhead (Fig. 25.1.1, bottom right), is implemented in 65nm CMOS. It features: 1) a 0.00182% native bit error after lossless stabilization and 0.44% across the military temperature range (-55 to 125°C); 2) a low-cost stabilization scheme combining a reconfigurable PUF cell with a body-bias-based V/T emulation method, which improves bit error rate (BER) by 149× and bit instability by 120×; 3) sub-threshold operation with only 0.062fJ/b core energy.