Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate-Stack

High-performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm
²
/
$\text{V}\,\cdot $
s, and a peak field effect mobility of 154 cm
²
/V s, in 2-
$\mu $
m gate length MOSFETs. The gate-stack was designed to minimize interface states and comprised a 0.7-nm thermally grown SiO
₂
on 4H-SiC, followed by Al
₂
O
₃
and a metal gate contact. In this way, carbon remaining following SiC oxidation is significantly reduced. A density of interface traps in the range of
$6 \times 10^{11} - 5 \times 10^{10}$
cm
⁻²
eV
⁻¹
is also obtained. Temperature-dependent electrical data reveal that the high mobility results from conduction being phonon-limited, rather than Coulomb-limited. Furthermore, universal mobility in these 4H-SiC MOSFETs is shown to be up to 50% of that observed in the Si devices. Expressions for electric field-dependent contributions to mobility are presented. A steep subthreshold slope of 127 mV/decade indicates low electrical defect density. A temperature coefficient of −4.6 mV/K in threshold voltage is similar to that in the Si MOSFETs.