Squarer and Sinusoidal Frequency Doubler Based on Single OTRA

In this paper, a simple circuit design technique for realizing analog squarer is proposed. Its extension as sinusoidal frequency doubler has also been discussed. The proposed circuit uses single operational trans-resistance amplifier, two n-channel MOS transistors and one resistor. If the resistor is replaced by two n-channel MOS transistors then the circuit is fully suitable for monolithic integration. In the proposed circuit the power consumption and total harmonic distortion are found 0.743μW and 1.2% respectively. The performance of the proposed squarer and frequency doubler circuit are verified through PSPICE simulators using 0.5μm CMOS technology parameter provided by MOSIS (AGILENT). The simulation result confirms the feasibility of the proposed circuit.