Improved Performance in GeSn/SiGeSn TFET by Hetero-Line Architecture With Staggered Tunneling Junction

Vertical tunneling FET utilizing hetero-line architecture with GeSn/SiGeSn staggered tunneling junction (TJ) is designed and theoretically characterized. Utilizing vertical spacer etching and selective growth techniques, p⁺ GeSn source/n⁺ SiGeSn pockets line tunneling can be realized, which strengthens the boosting effect of staggered TJ. It is demonstrated that, in addition to reducing the tunneling barrier by increasing Sn composition, the device performance can be improved by optimizing length and thickness of n⁺ SiGeSn pocket.