A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency

In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming voltage is realized by inserting the SiGe QW beside the drain. This QW also functions as the storage node, which enhances not only the current sensing margin but also the retention time (τ
_ret
) compared with those of all-Si device. At an extremely scaled cell size and sub-10-ns write/erase operations, the proposed device shows 0.2-s-long τ
_ret
and current ratio > 10
⁴
. It has been verified that a single cycle of 1T DRAM operations consumes only 93.8 fJ.