Active Device Performance after Fan-out Wafer-level Packaging Process

For the study of active device effect by fan-out wafer level packaging process, fan-out assembly processes were simulated by using actual CMOS device wafers as carrier to study the device performance effect. The I
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and I
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of 65nm technology node NMOS and PMOS devices were characterized before and after fan-out wafer level packaging process, respectively. The thermal cycle testing for the active device was carried out for the wafers with 20μm and 10μm Si substrate.