Enabling Pb-Free Flip Chip QFN Technology: Understanding Kirkendall Voiding and Factors Affecting Its Formation During Bump Process

Previous comprehensive studies like those by Mei et al. and Kim et al. have posted significant milestones in understanding the phenomenon of Kirkendall voiding (KV) and their behavior through various conditions of reliability testing and reflow on Ball Grid Array (BGA) technologies. [1,2] This paper presents results under constant conditions with regard to temperature cycling (-55/125°C) and high temperature bake (170°C and 200°C) specifically for Flip Chip Quad Flat No-Lead (QFN) technologies. The consolidation of this study in union with previous studies has shown that there is an utmost significance in mitigating Kirkendall void formation at its source, so that its necessity for control through various reliability conditions can be streamlined. Microvoid formation, then, was studied with respect to impurities situated at the Cu-Sn alloy intermetallic compound (IMC) induced during the bumping process. It was observed through design of experimentation (DOE) that an oxygen (O₂) descum step in between a short Cu-Sn alloy electroplating window time yielded the best results of 75% improvement on KV density (%KV), 11% on minimum KV distance and 56% on maximum KV size at time zero (T0). Recommendations include exploring the phenomenon's behavior with the inclusion of a metal barrier, and varying alloy concentrations to be also subjected to extended thermal aging and cycling.