Power Integrity Analysis for Active Silicon Interposer

Active silicon interposer (ATSI) was developed to reduce system cost as well as provide wide bandwidth. ATSI package is targeting to accommodate large FPGA with wide I/O. The power integrity of the ATSI is analyzed. The power distribution network (PDN) in the package includes metallic mesh network, TSV and ball grid array (BGA). The line width and the gap of the mesh network are chosen as 75 μm and 25 μm. Small slots are added in the metal line in order to meet the metal density requirement. Six TSVs are designed to connect the metallic mesh network to one BGA through the backside RDL. MIM capacitors are specially embedded under the top metallic layer near the chip micro bump to reduce the PDN impedance. A portion of the PDN with size of 2.4×2.4 mm
²
is modelled and simulated to estimate the performance of the whole PDN structure.