Development of Resolution Scalable Successive Approximation Register ADC in 90nm CMOS Process Technology for Wireless Sensor Network

Wireless Sensor Network (WSN) for environmental monitoring in a form of a sensor platform is built with individual nodes, called sensors, that accepts analog signals detected from the changes of state in the environment. One of the crucial parts of a WSN is an Analog-to-Digital Converter (ADC) which acts as the interface between the environment and the platform. Since the WSN is for environmental monitoring, it is powered by an energy harvesting unit which demands for low-energy consumption on the constituent blocks including the ADC. Implementing a high-resolution converter can mean higher energy consumption and a much accurate digital result, nonetheless, lower resolution converter consumes less energy but still can give correct digital output. This trade-off between accuracy and energy consumption made impact to the researchers to develop a programmable Successive Approximation Register ADC for WSN. This research study was implemented using Synopsys EDA Tool in 90nm CMOS Process Technology. The SAR ADC was successfully designed with 8-bits and 14-bits resolution, a sampling rate of 100ksps and 62.5ksps, respectively. The energy consumption of the SAR ADC is 234pJ (8-bits) and 366.72pJ (14-bits), and an energy saving of 36.2%.