Development of Low Power Full-Custom 1 Kb 8T Synchronous SRAM for Wireless Sensor Network in 90nm CMOS Process Technology

The aftermath of endless environmental degradation poses a lot of risk among individuals including climate change. Modern technology addresses the need of a more competent environmental monitoring through Internet of Things (IoT) and the use of System-on-Chips (SoCs) such as Environmental Sensor Platform. One of the critical components of SoC is a Random Access Memory (RAM) which presents a sizable fraction of power consumption. This makes memory inappropriate for energy-constrained applications such as environmental monitoring. The purpose of this study is the development of low power full-custom 8T SRAM for sensor platforms. Different SRAM topologies were evaluated to identify which among has the lowest power consumption. Verified through simulations, a fully functioning schematic that can read and write data were designed in 90nm CMOS process technology. Layout of each block were created using Synopsys design tools yielding power consumption of 21.0405mW and static noise margin of 520mV achieved by eliminating sense amplifier and pre- charge circuits. This study significantly reduced power consumption of memory which is suitable for environmental monitoring applications.