Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors

Hardware security vulnerabilities are a major concern for embedded computing devices which are now used in many application such as credit cards, SIM cards, or financial systems, putting sensible data at risk. Such systems are often targeted by differential power attacks, where the power trace can be monitored in order to get access to the sensible data. To alleviate this issue, a possible technique proposed in literature is to use a complementary gate (e.g., computing both XOR and XNOR operations in parallel) in order to have a symmetrical power trace for all possible input combinations. However, this technique results in a large area and power overhead since it approximatively requires twice the number of transistors. Recently, novel technologies such as Three-Independent-Gate Field Effect Transistors (TIGFETs) have been shown to be able to realize compact logic gates using less transistors when compared to Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we investigate the benefits of using TIGFETs in terms of hardware security. First, we show that using the complementary gate technique with TIGFETs can reduce the transistor count, the power trace variation, the switching power and leakage by 2×, 57%, 36% and 8× respectively, when compared to CMOS. In addition, we show that for the same transistor count and similar switching power, using TIGFETs can reduce the power trace variation and the leakage by 81% and 6.7× respectively when compared to CMOS.