An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOS

We present a digitally intensive adaptive-resolution (AR) quasi-level-crossing-sampling (quasi-LCS) analog-to-digital converter (ADC) for Internet-of-Things wireless networks, where the power consumed in data transmission, processing, and storage can be significantly reduced by minimizing the ADC's gross output bit-rate. The AR quasiLCS ADC is implemented as a delta-modulator and adopts a 4-bit asynchronous SAR ADC to quantize the residue voltage signal, thus allowing a straightforward implementation of LCS and AR algorithms in the digital domain, as well as yielding a digital-friendly architecture. Fabricated in 28-nm CMOS, this ADC achieves an SNDR of 53dB over 1.42 MHz signal bandwidth while consuming 205 μW and an active area of 0.0126 mm
²
.