Experimental Power and Performance Evaluation of CAESAR Hardware Finalists

In 2013 the Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR) was started. It aims at determining a portfolio of ciphers for authenticated encryption that has advantages over AES-GCM in terms of performance, security, and ease of implementation. This competition, for the first time, provides a standardized hardware API, which allows a fair comparison of hardware implementations. In this work, we extend a opensource evaluation platform using the CAESAR-API in a Xilinx Zynq-7000 System on Chip (SoC) with ARM processors and an AXI interface to support on-chip power measurement and dynamic frequency scaling. We then show the applicability of our measurement setup, giving results for the CAESAR finalists and finally pointing out some bugs in the latest official reference implementations.