IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado

Dynamic partial reconfiguration is considered a great technique to increase flexibility in FPGA designs. However, partial reconfiguration flows supported by commercial tools, such as Xilinx Vivado, still have many limitations. Foremost among them are the lack of support for relocation, which leads to an increase in the on-system memory requirements and the synthesis time, as well as a reduced flexibility when it comes to the definition of reconfigurable regions. Several academic tools have appeared over the years to improve commercial flows. However, the technology shift from ISE to Vivado has left most of these tools unusable for newer FPGAs, including most of the Xilinx Series-7 devices. In this paper, authors present IMPRESS, a TCL script-based tool for the automated generation of relocatable partial bitstreams under Vivado, with a strong focus on the ease of use and the system flexibility. Special support is provided for the implementation of reconfigurable systems that include IP blocks generated with Vivado HLS and standardized bus interfaces. A stream-based reconfigurable architecture for image filtering, implemented in a fully automated manner on a Zynq SoPC, is provided as a use case of the tool.