Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures

This brief presents an on-chip autotuning algorithm to reduce the supply voltage sensitivity of digitally controlled delay lines constructed using identical digital buffers. The proposed algorithm tunes a compensator circuit embedded within each buffer to counterbalance the supply sensitivity of the overall delay line regardless of process or mismatch variations. A 3-D IC mismatch-insensitive skew compensation (MISC) architecture employing this delay line is fabricated in 65-nm CMOS and demonstrates robust performance against the buffer supply noise at operating frequencies of 250 MHz to 1 GHz. The rms jitter of this supply-compensated MISC design measures 3 ps in the presence of a 25-mV 1-MHz supply noise at 1-GHz operation, compared to 112.3 ps for the conventional design, whereas the maximum residual skew between the Die-1 and Die-2 clocks measures under 30 ps across the entire MISC frequency range.