TSV Induced Stress Model and Its Application in Delay Estimation

Through Silicon Vias (TSVs) used in 3D ICs induce stress in the silicon wafer. This stress causes variations in the mobility and threshold voltage depending upon the value of various stress components, which in turn affects the propagation delay of logic gates. In this paper, a complete methodology is developed for modeling the variation of an inverter and a 2-input NAND gate delay at any point (r, θ) around a TSV. Analytical models for stress variations are developed, subsequently, the corresponding variations in mobility and threshold voltage are modeled. These variations are translated into the delay variations using the timing models developed. We show that due to TSV induced stress an Inverter and NAND gate delay varies around 20%. The proposed model predicts this variability with a maximum error of around 9%.