Finite Element Method (FEM) simulation based analysis for optimal chip layout of a 2.5D flip chip package

The current paper describes finite element method based simulations to assess assembly process and thermo-mechanical reliability related risks associated with 2.5D flip chip package and to develop guidelines for an optimal chip layout of a 2.5D package. A general configuration of a 2.5D package includes a silicon interposer on which logic and memory die are placed. In this study, the relative location of the top die, interposer edges and its impact on the mechanical performance of the package is investigated. Two different phases of module assembly are analyzed: 1. Post chip/interposer reflow attach prior to under fill application and 2. Post final assembly. The 2.5D package incorporates fine-pitch copper pillar interconnects on the logic die along with conventional C4 bumps on the interposer which are susceptible to damage during thermal excursions. The plastic strains in these structures are analyzed to assess risk of damage. Die-under fill shear stress is utilized as a metric to study the potential for under fill delamination during thermal cycling.