A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors

The placement of bottom tier blocks under top-tier inductors could significantly improve the area-efficiency of M3D RF/AMS circuits, paving the way for new applications of this integration technology. This work investigates the potential of placing digital blocks in the bottom tier, underneath top tier inductors. A design-technology co-optimization flow is applied and a number of design guidelines are suggested. These guidelines ensure high electromagnetic isolation between the two tiers, with minimum penalties on the loading of bottom tier wires, as well as on the inductor's performance.