Interpolating time counter with 100 ps resolution on a single FPGA device

This paper describes the logic and performance of an interpolating time counter integrated on a single FPGA device. The resolution of 100 ps (LSB) was obtained because of the new design of the FPGA delay lines used for precise time-to-digital conversion, and the use of enhanced CMOS FPGA technology. The worst-case random error of 170 ps has been lowered to 70 ps by software correction of the nonlinearity of the delay lines. The counter can measure time intervals from 0-43 s and frequency up to 200 MHz. The maximum power consumption of the counter chip is 260 mW.