Mixed Operating Mode of CMOS Digital Circuits

Novel precise limitations and terms of CMOS digital logic circuits operation modes are proposed. These are not to be confused with the transistor operating modes, i.e. inversion regions. As already known, if the circuit's supply voltage, V
_dd
, is lower than the transistor threshold voltage, V
_tn
or V
_tp
, the circuit operates in the sub-threshold mode. For the supply voltage ranges of V
_tn
<;V
_dd
<;V
_tn
+|V
_tp
| and V
_dd
>V
_tn
+|V
_tp
| the terms mixed operating mode and above double threshold operating mode are proposed. It is shown that the analytical models of switching threshold and dissipation due to direct-path current of an inverter operating in the mixed mode are equal to those in sub-threshold mode. Further, rise and fall times of the inverter operating in the mixed mode, are modeled by the same equations used in the above double threshold regime. Within this paper, it is also shown that the minimum of power-delay product is found around the mixed mode midpoint. A tabular review of analytical models of basic inverter parameters in all three CMOS operating regimes is given.