Implementation of Visible Light Communication using PAM on Xilinx Artix 7 35T FPGA

In this paper, m-ary PAM is implemented on Arty board of Artix 7 35T, with the objection of creating a VLC system. PAM is used to fulfil VLC requirement of real-positive signal processing without imaginary parts. The signal processing was created first in Simulink and synchronized with System Generator. The PAM system design created was then generated to FPGA using Vivado Design Suite. Variations of PAM including 4, 8 and 16-PAM are compared. The system are simulated with and without DC bias component. Observations are made upon the FPGA performance in running the system design, i.e. resource usage, power and time constraint. From the implementation result, the system design of VLC with 4 PAM without DC biased used less resources power and time constraintwith LUT <; 0.005% and I/O Block <; 2.3%, while 16 PAM with DC bias needs more resource.