Synthesis of Compact Crossbars for in-Memory Computing using Dynamic FBDDs

Computer-aided synthesis benefits from algorithms that are capable of designing compact circuits. This paper is an attempt to improve area and time efficiency of crossbars synthesized using Free Binary Decision Diagrams (FBDDs). We report 13.7% and 6.2% improvement in area and time requirements of multiplier crossbars synthesized using FBDDs. We have used Dynamic Weight Heuristic (DWH) to make FBDDs more compact than the previous approach. Our approach is not multiplier specific; we have found it to perform better than the previous FBDD based synthesis for other RevLib benchmarks as well.