Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

The main purpose of this paper is to achieve as low as possible leakage current (I
_OFF
) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths L
_eff
, gate stacks, gate contact materials, and gate-sidewall spacers (L
_sp
). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length L
_sp
and LHK is investigated to get low leakage current keeping I
_ON
/I
_OFF
as high as possible. Moreover, the effective channel length in subthreshold conduction (L
_eff
) is maintained greater than the gate length (L
_g
) and the threshold voltage (V
_th
) is adjusted by the proper metal gate work function. The performance of the proposed nand p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted I
_OFF
is 17 pA/μ m for n-FinFET and 14.7 pA/μm for p-FinFET which are the lowest leakage currents found in recent publications. The achieved I
_ON
/I
_OFF
ratio for both proposed devices is found to be 12.3 x 10
⁶
and 11 x 10
⁶
, respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of L
_sp
= 10 nm and L
_HK
= 5 nm. In addition, the short channel effects variations with LHK have been investigated.