Improving Diagnosis Efficiency via Machine Learning

Logic diagnosis, the process of identifying and locating possible defects in failing integrated circuits, is a key step in yield learning for both technology development and high-volume manufacturing. However, resources can be easily wasted if diagnosis results in no meaningful information, or if the type of diagnostic result is not actionable. It would therefore be very beneficial to have a comprehensive preview of diagnostic outcomes beforehand, which allows diagnosis resources to be prioritized in a more reasonable and effective way. In this work, a methodology is developed to predict whether a fail log for a given design will result in a diagnosis outcome that is meaningful for the purpose at hand. Specifically, the aim is to predict the time required for diagnosis, and whether diagnosis produces any defect candidates, and if so, are those candidates the result of logic failure or chain failure. Random Forest classification algorithm is used for prediction. Experiments on a 28nm test chip and a high-volume 90nm part illustrate that the methodology can provide accurate prediction results (0.95+ precision, 0.9+ recall and F1-score, and 0.96+ AUC on average) when two classes are balanced, and satisfactory results (0.95+ recall and 0.98+ AUC on average) when two classes are imbalanced.