An Inverter-Based Analog Front-End for a 56-Gb/s PAM-4 Wireline Transceiver in 16-nm CMOS

This letter describes an inverter-based analog receiver front-end that was evaluated within a complete ADC-based 56-Gb/s four pulse-amplitude modulation wireline transceiver system. The frontend contains hybrid continuous-time linear equalizers with lowand high-frequency peaking as well as inverter-based programmable gain amplifiers that serve as buffers for the 32× time-interleaved SAR ADC. The inductorless design achieves high bandwidth through a reduced number of equalizer stages (with fewer parasitic poles) and active peaking techniques. The transceiver that contains the analog front-end (AFE) achieves . 10-6 BER over a backplane channel with 35-dB loss at 14 GHz and with 2-mVrms input crosstalk noise. The AFE core occupies 0.00425 mm
²
in 16-nm fin field effect transistor CMOS and consumes 165 mW.